Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming of a charge storage structure, such as floating gates or trapping layers or other physical phenomena, determine the data state of each cell. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, cellular telephones, and removable memory modules, and the uses for flash memory continue to expand.
FIG. 1 illustrates a typical prior art programming operation for a memory cell in a series string of memory cells of a NAND architecture memory device. The memory cells of the series string are coupled in series drain-to-source. A source-side of the series string is coupled to a source line through a select gate source transistor 101. A drain-side of the series string is coupled to a bit line through a select gate drain transistor 102.
The control gate of a selected memory cell 100 is biased at Vpgm as a cell having a control gate that is commonly coupled with the selected memory cell is being biased at Vpgm to program that particular memory cell. The control gates of memory cells 105, 106 on either side of and adjacent to the selected memory cell 100 are biased at a cut-off voltage (e.g., VSS) so that these memory cells are turned off to act as cut-off memory cells that provide a local self-boost. The control gates of the remaining transistors of the series string are biased at a Vpass voltage that enables these memory cells to act in a pass through mode.
One problem with this programming inhibiting is that when a series string comprises a large number of erased memory cells between the selected memory cell and the select gate source, a large capacitance C exists in the channel of the source-side memory cells. The large capacitance causes a leakage current (ILEAK) from the selected memory cell channel to the large capacitance C. The leakage current can reduce the voltage of the channel of the cell 100 being program inhibited, thus increasing the possibility of programming errors.
For the reasons stated above and for other reasons that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a reducing source-side channel capacitance in a string of memory cells.